✅ With the latest revision this PR passed the undef deprecator.

This triggers failed asserts when compiling for ARM:

short *ScaleUVRowDown2_C_src, *ScaleUVRowDown2_C_dst;
int ScaleUVRowDown2_C_x;
void ScaleUVRowDown2_C() {
  for (; ScaleUVRowDown2_C_x; ScaleUVRowDown2_C_x += 2) {
    ScaleUVRowDown2_C_dst[0] = ScaleUVRowDown2_C_src[1];
    ScaleUVRowDown2_C_dst[1] = ScaleUVRowDown2_C_src[3];
    ScaleUVRowDown2_C_src += 2;
    ScaleUVRowDown2_C_dst += 2;
  }
}

$ clang -target armv7-linux-gnueabihf -c repro.c -O2
clang: ../include/llvm/ADT/ArrayRef.h:253: const T& llvm::ArrayRef<T>::operator[](size_t) const [with T = int; size_t = long unsigned int]: Assertion `Index < Length && "Invalid index!"' failed.

Also, note the commit https://github.com/llvm/llvm-project/commit/9115bef8ee1d9a47fef3221d9f3e0fd5c4ed947c.patch ended up with a hidden email. Please turn off Keep my email addresses private setting in your account. See LLVM Developer Policy and LLVM Discourse for more information.

This triggers failed asserts when compiling for ARM:

short *ScaleUVRowDown2_C_src, *ScaleUVRowDown2_C_dst;
int ScaleUVRowDown2_C_x;
void ScaleUVRowDown2_C() {
  for (; ScaleUVRowDown2_C_x; ScaleUVRowDown2_C_x += 2) {
    ScaleUVRowDown2_C_dst[0] = ScaleUVRowDown2_C_src[1];
    ScaleUVRowDown2_C_dst[1] = ScaleUVRowDown2_C_src[3];
    ScaleUVRowDown2_C_src += 2;
    ScaleUVRowDown2_C_dst += 2;
  }
}

$ clang -target armv7-linux-gnueabihf -c repro.c -O2
clang: ../include/llvm/ADT/ArrayRef.h:253: const T& llvm::ArrayRef<T>::operator[](size_t) const [with T = int; size_t = long unsigned int]: Assertion `Index < Length && "Invalid index!"' failed.

This seems to be a bug in the ARM backend. The generated shufflevector is valid (see below), but the function isVTRNMask in ARMISelLowering.cpp assumes the mask size is equal to, or exactly double, the size of the input vector.

%17 = load <15 x i16>, ptr %16, align 2, !tbaa !9
%18 = getelementptr inbounds nuw i8, ptr %next.gep, i32 6
%19 = load <15 x i16>, ptr %18, align 2, !tbaa !9
%interleaved.vec = shufflevector <15 x i16> %17, <15 x i16> %19, <16 x i32> <i32 0, i32 15, i32 2, i32 17, i32 4, i32 19, i32 6, i32 21, i32 8, i32 23, i32 10, i32 25, i32 12, i32 27, i32 14, i32 29>

This seems to be a bug in the ARM backend. The generated shufflevector is valid (see below), but the function isVTRNMask in ARMISelLowering.cpp assumes the mask size is equal to, or exactly double, the size of the input vector.

%17 = load <15 x i16>, ptr %16, align 2, !tbaa !9
%18 = getelementptr inbounds nuw i8, ptr %next.gep, i32 6
%19 = load <15 x i16>, ptr %18, align 2, !tbaa !9
%interleaved.vec = shufflevector <15 x i16> %17, <15 x i16> %19, <16 x i32> <i32 0, i32 15, i32 2, i32 17, i32 4, i32 19, i32 6, i32 21, i32 8, i32 23, i32 10, i32 25, i32 12, i32 27, i32 14, i32 29>

CC @davemgreen @DavidSpickett

Even if this is an unrelated backend bug, I'd like to revert this change, that exposes the preexisting issue, in order to get back to green until we have the backend bug fixed.

I'll take a look.